代码代写｜LAB 4 : Single-Cycle CPU

itcs％1 $ S

这是一篇美国的Verilog实现CPU指令含报告代码代写

 

  1. Goal
  • To realize how to set the control signal in different instruction type.( Decoder & ALU Controller)
  • To clarify how sign-extend work.
  • Connect all datapath to form a single cycle CPU
  1. HW Requirement
  • Implement bellow instruction for testing data(80%)

○ add

○ slt

○ addi

○ lw

○ sw

○ jal

○ jalr

○ You would not get any score for this part if you

program can’t pass the test by script.

  • Report(20%)
  1. Hand in
  • $(groupN)_$(studentid1)_$(studentid2).zip

○ $(groupN)_$(studentid1)_$(studentid2)

■ report.pdf

■ {*.v}

  • Your report should be in PDF format.

(one report per group)

  1. Grade

Single Cycle CPU (80%)

Report (20%)

  • Detailed description of the implementation● Implementation results
  • Problems encountered and solutions

❖ Late submission: 10% penalty per day

❖ No plagiarism, or you will get 0 points

  1. Q&A
  • Feel free to ask on HackMD if you need.
  • We will not debug for you
  1. Reference
  • RISC V(https://riscv.org/technical/specifications/)

程序代写代做C/C++/JAVA/安卓/PYTHON/留学生/PHP/APP开发/MATLAB

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