数据库代写|INFO20003 Assignment 1: ER Modelling

这是一篇来自美国的组织和设计计算机代写

 

In the project, you just need to implement what was described in the honor option section in lab 5, with the addition of the implementation and generation of the bit stream without errors.

  1. Write a report that contains the following:

i.Your Verilog design code. Use:

i. Device: Zyboboard (XC7Z010- -1CLG400C)

ii. Your Verilog® Test Bench design code. Add “`timescale 1ns/1ps” as the first line of your test bench file.

iii. The waveforms resulting as requested from item 9 above.

iv. The design schematics from the Xilinx synthesis of your design. Do not use any area constraints.

v. Snapshot of the I/O Planning and

vi. Snapshot of the floor planning

vii. The design should be free from errors when synthesized, implemented and generated of the bitstream.

The report format will be as follows:

  1. REPORT FORMAT: Free form, but it must be:

a.One report per student.

b.Have a cover sheet with identification: Title, Class, Your Name, etc.

c.You have to write an abstract at the beginning of the project report to describe what you are doing in the project.

d.You should include an introduction for the project explaining with diagrams the connection between all the stages and what would be the benefit of using that architecture in the computer organization field.

e.Use Microsoft word and your report should be uploaded in word format not PDF. If you know LaTex,you should upload the Tex file in addition to the PDF file.

f.Single spaced

The following part is not mandatory but any student will choose to do this part in addition to the previous  part, will take 5 points extra to the total grade of the course:

In this extra points project, the students are implementing a pipeline CPU using the Xilinx design package for FPGAs. You can use any information available in previous labs if needed.

  1. Pipelining

As described in lab 3

  1. Circuits of the Instruction Fetch Stage

As described in lab 3

  1. Circuits of the Instruction Decode Stage

As described in lab 3

  1. Circuits of the Execution StagePenn State University

As described in lab 4

  1. Circuits of the Memory Access Stage

As described in lab 4

  1. Circuits of the Write Back Stage

As described in lab 5

  1. Control Hazards and Delayed Branch

The control hazard occurs when a pipelined CPU executes a branch or jump instruction. The jump target address a jump instruction (jr, j, or jal) can be determined in the ID stage and it will be written into PC at the end of the ID stage. But because the pipelined CPU fetches instruction during every clock cycle, the next instruction is being fetched during the ID stage of the jump instruction. The control hazard caused by a conditional branch instruction (beq or bne) becomes more serious than that of a jump instruction because the condition must be evaluated in addition to the calculation of the branch of the target address. Figure 1 shows an example when we calculate the branch target address in the EXE or the ID stage respectively. There are mainly two methods to deal with the instruction(s) next to branch or jump instruction. One method is to cancel it (them). The other is to let it (them) be executed. The second method is called a delayed branch. The position in between the location of a jump or branch instruction and the jump or branch target address are called delay slots. MIPS (microprocessor without interlocked pipeline stages) ISA (instruction set architecture) adopts a one delay slot mechanism: the instruction located in delay slot is always executed no matter wither the branch is taken or not as shown in figure 2. In figure

2 (a) shows the case where the branch is not taken. Figure 2 (b) shows the case where the branch is taken; t is the branch target address. In both cases, the instruction located in a+4 (delay slot) is always executed no matter whether the branch is taken or not. In order to implement the delayed branch with one delay slot, we must let the conditional branch instructions finish the executions in the ID stage. There should be no problem for calculating the branch target address within the ID stage. For checking the condition, we can perform an exclusive OR (XOR) on the two source operands:

rsrtequ = ~ | (da^db); // (da == db)

where the rsrtequ signal indicates where da or db are equal or not. Both da and db should be the state of the art data. Referring to figures 3 and 4, we use the outputs of the multiplexers for internal forwarding as da and

  1. This is the reason why we put the forwarding to the ID stage instead of to the EXE stage. Because the delayed branch, the return address of the MIPS jal instruction is PC+8. Figure 5 illustrates the execution of the jal instruction. The instruction located in delay slot (PC + 4) was already executed before transferring control to a function (or a subroutine). The return address should be PC+8, which is written into $31 register in the WB stage by the jal instruction. The return form subroutine can be done by the instruction of jr $31. The jr rs instruction reads the content of register rs and writes it into the PC.