# 计算机代写｜EGEC 540 Computer Arithmetic Structures Exercise 1

## Exercise 1

1. Add +5 and +6 in binary using the signed 1’s complement representation/format. Assume width of 4 bits. Comment on the result and give reasons wherever applicable
2. Repeat problem 1 with a width of 5 bits
3. Add −2 and −6 in binary using the signed 1’s complement representation/format. Assume width of 4

bits. Comment on the result and give reasons wherever applicable

4. Repeat problem 3 with a width of 5 bits
5. Add −2 and −6 in binary using the signed 2’s complement representation/format. Assume width of 4

bits. Comment on the result and give reasons wherever applicable

6. Repeat problem 5 with a width of 5 bits
7. Answer this question in the context of the IEEE 754 format for representing floating point numbers:

I. Give the value of the largest positive normalized number that can be represented in this format. Assume total width of 32 bits.

II. Give the value of the largest positive denormalized number that can be represented in this format. Assume total width of 32 bits.

## Exercise 2

1. Design the Moore finite state machine for a serial adder and sketch the block-level logic diagram for a 4-bit serial adder.
2. Find the overall worst-case delay (e. the delay at which all the outputs of the circuit are finalized) for each of the unsigned adder circuits mentioned below (carry-in to the first bit position=0 in each case). Assume that the delay due to one level of gates is D. Also, assume that inverted versions of signal variables are already available (i.e. ignore inverter delays). Furthermore, assume unlimited fan-in unless specified otherwise.

III. 8-bit global CLA (GCLA) assuming fan-in limit of 4 IV. 8-bit global CLA (GCLA) assuming fan-in limit of 8

3. Find the overall worst-case delay (e. the delay at which all the outputs of the circuit are finalized) for

each of the unsigned adder circuits mentioned below (carry-in to the first bit position=0 in each case). Assume that the delay due to one level of gates is D. Also, assume that inverted versions of signal variables are already available (i.e. ignore inverter delays). Furthermore, assume unlimited fan-in unless specified otherwise.

1. 16-bit block CLA (BCLA) with block size=8
2. 16-bit block CLA (BCLA) with block size=4
3. 16-bit block RCA-BCL adder with block size=8
4. 16-bit block RCA-BCL adder with block size=4
5. 16-bit block carry-skip adder (CSA) with block size=2
6. 16-bit block carry-select adder (CSelA) with block size=4. Assume that the first block is

implemented as an RCA

4. For the unsigned addition of the given bit-pattern pair, identify the overall delay (e. the delay at which all the outputs of the circuit are finalized) experienced in the case of each unsigned adder circuit mentioned below (carry-in to the first bit position=0 in each case). Assume that the delay due to one level of gates is D. Also, assume that inverted versions of signal variables are already available (i.e. ignore inverter delays). Furthermore, assume unlimited fan-in.

0010101001101110 1100101110100011

I. RCA II. CCA

III. BCLA with block size=8
IV. RCA-BCL adder with block size=8

V. CSA with block size=2
VI. CSelA with block size=8. Assume that the first block is implemented as an RCA

5. For each of the signed adder/subtractor circuits mentioned below, find the overall worst-case delay (e. the delay at which all the outputs of the circuit are finalized). Assume that the core unsigned adder is implemented using RCA logic in each case. Assume that the delay due to one level of gates is D. Also, assume that inverted versions of signal variables are already available (i.e. ignore inverter delays). Furthermore, assume unlimited fan-in.