计算机结构代写 | CSE-141L Lab 1 9-Bit Instruction Set Architecture

本次cs代写主要为计算机结构相关的lab

1. Overview

In this lab, you shall design the instruction set and overall architecture for your own
special-purpose (very) reduced instruction set (RISC) processor. You will design the
hardware for your processor core in subsequent labs.

Your processor shall have 9-bit instructions (machine code) and shall be optimized for
three simple programs, described below. For this lab, you shall design the instruction set
and instruction formats and code three programs to run on your instruction set. Given
the tight limit on instruction bits, you need to consider the target programs and their
needs carefully. The best design will come from an iterative process of designing an ISA,
then coding the programs, redesigning the ISA, etc. Your instruction set architecture
shall feature xed-length instructions 9 bits wide. Your instruction-set speci cation
should describe:

• What operations it supports and what their respective opcodes are. For ideas, see
MIPS or ARM instruction lists

• How many instruction formats it supports and what they are (in detail { how many
bits for each eld, and where they’re found in the instruction). Your instruction
format description should be detailed enough that someone could write an assembler
(a program that creates machine code from assembly code) for it. (Again, refer to
ARM or MIPS.)

• Number of registers, and how many general-purpose or specialized. All internal
data paths and storage will be 8 bits wide.

• Addressing modes supported (this applies to both memory instructions and branch
instructions). That is, how are addresses constructed or calculated? Lookup tables?
Sign extension? Direct addressing? Indirect, as used in linked lists or ARM or
MIPS to address the data memory from reg le contents?

For this to t in a 9-bit eld, the memory demands of these programs will have to be
small. For example, you will have to be clever to support a conventional main memory
of 256 bytes (8-bit address pointer). You should consider how much data space you
will need before you nalize your instruction format. Your instructions are stored in
a separate memory, so that your data addresses need be only big enough to hold data.

Your data memory is byte-wide, i.e., loads and stores read and write exactly 8 bits (one
byte). Your instruction memory is 9 bits wide, to hold your 9-bit machine code, but it
can be as deep as you need to hold all three programs.

You shall write three programs on your ISA. You may assume that the rst starts
at address 0, and the other two are found in memory after the end of the rst program
(at some nonoverlapping address of your choosing). The speci cation of your branch
instructions may depend on where your programs reside in memory, so you should make
sure they still work if the starting address changes a little (e.g., if you have to rewrite
one of the programs and it causes the others to also shift). This approach will allow you
to put all three programs in the same instruction memory later on in the quarter.
We will impose the following constraints on your design, which will make the design
a bit simpler.

• Your ALU instructions will be comparable in complexity to those in ARM.

• You may also have a single ALU condition/ ag register (e.g., carry out, or shift
out, sign result, zero bit, etc., like ARM’s Z, N, C, and V status bits) that can be
written at the same time as an 8-bit register, if you want.

• Your data memory (Verilog design will be provided) is byte-addressable, and will
have only one address pointer input port, for both input and output.

• Your register le (or whatever internal storage you support) will have no more than
two output ports and one input port. You may use separate pointers for reads and
writes, if you wish. Please restrict register le depth to no more than 16 registers.

• Manual loop unrolling of your code is not allowed.

• You may use lookup tables (LUTs) / decoders, but these are limited to 32 elements
each (i.e., address pointer width up to 5 bits). We do not allow something like
a 512-element LUT with 32-bit outputs which simply maps your restricted 9-bit
machine code eld to a 32-bit clone of ARM or MIPS instructions.


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