Pipesim was developed with the sole purpose of teaching computer architecture.
Note that Pipesim is still under development and has limited feature sets.
Future extensions of Pipesim functionality are left to you.
Pipesim source code overview
Pipesim consists of 3 main fles:
- ( main. cpp ) initializes the pipeline and loads the instruction trace to run.
- ( pipeline.h ) contains the class defnitions for various objects.
- ( pipeline.cpp ) implements the main functionality of the pipeline timing simulator (only file you need to modify!).
*** DO NOT MODIFY main. cpp ) OR pipeline.h !
Functions of interest are, but not limited to, the following:
bool Pipeline: :hasDependency(void)
。Checks for hazards between the instruction in the decode stage and execute/memory/writeback stage.
void Pipeline:: cycle(void)
。Simulates the flow of instructions through the pipeline.
。Currently stalls the pipeline if RAW hazards are detected.
The following shows an example run of Pipesim. Pipesim prints out the flow of the instructions through a 5-stage pipeline. Pipesim currently supports sallig to resolve RAW hazards.
Pipesim takes in two command line parameters:
$./pipesim -i <fileName> -f
-i <fileName> : to run input file fileName
-f : for enabling forwarding
Input File (-i <fleName>):
。The input fle is a sequence of instruction that will be simulated through the pipeline.
。We provide three sample inputs in the traces folder (i.e., fleName):
。The forwarding option sets a flag to enable/disable forwarding.
。Currently, forwarding is not implemented.
。You will be implementing forwarding for this lab.
Pipesim minimal ISA
The input instruction format uses a minimal ISA format that includes all the information we need to model the timing of the pipeline. (All we really need are registers to detect RAW
hazards.) Currently, the ISA does not support immediate values, offset addressing, branches, etc.
For example, LW R1, 100(R2) is simplifed to (LW R1 R2
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