CS代写|CS-UY 2214 — Project 3

本次美国代写是一个e20缓存模拟器相关的assignment

1 Introduction

This project represents a substantive programming exercise. Like all work for this class, it is to be completed
individually: any form of collaboration is prohibited, as detailed in the syllabus. This project is considered
a take-home exam.

Before even reading this assignment, please read the E20 manual thoroughly. Read the provided E20
assembly language examples.

If you have not completed your E20 simulator, please do so before beginning this assignment.

2 Assignment: Cache simulator

Your task is to write an E20 cache simulator: a program that will monitor the effects that an E20 program’s
execution has on a memory cache. This project will build on your E20 simulator, by adding a simulated
cache subsystem.

Your simulator will be given a cache configuration, specifying the number and type of caches. Your
simulator will support up to two caches. Therefore, your program should be prepared to accept a cache
configuration with either just an L1 cache, or both an L1 and an L2 cache.

Each cache will be defined by three parameters, given as integers: the size of the cache, the cache’s
associativity, and the cache’s blocksize (measured in number of cells):

cache size

The total size of the cache, excluding metadata.
The value is expressed as a multiple of the size
of a memory cell. This will be a positive integer
power of 2 that will be at least the product of the
associativity and blocksize.

cache associativity

The number of blocks per cache line. This will
be an integer in the set {1, 2, 4, 8, 16}. An asso
ciativity of 1 indicates a direct-mapped cache. If
the product of the associativity and the blocksize
is equal to the cache size, and the associativity is
greater than 1, then the cache is fully associative.

cache blocksize

The number of memory cells per cache block. This
will be an integer in the set {1, 2, 4, 8, 16, 32, 64}.

Your simulator will monitor the effects on the cache or caches while executing an E20 program. The
output of your simulator will be a log of all cache hits and cache misses, in chronological order, caused by
all executed lw and sw instructions.

• When an sw instruction is executed, the log will be appended with a line indicating so, along with the
current value of the program counter, the memory address that was written, and the cache line where
the data was cached. The format is as follows:

L1 SW pc: 2 addr: 100 line: 4

If there are two caches, then the write to both affected caches should be logged separately, as follows:

L1 SW pc: 2 addr: 100 line: 4
L2 SW pc: 2 addr: 100 line: 0

In the above case, the data was written to both L1 and L2, as dictated by a write-through policy.

• When an lw instruction is executed, the log will be appended with a line indicating so, along with
whether the memory read was a hit or a miss, the current value of the program counter, the memory
address that was written, and the cache line where the data was cached. The format is as follows, in
the case of a miss:

L1 MISS pc: 22 addr: 128 line: 4

Alternatively, in the case of a hit, you should indicate that there was a hit:

L1 HIT pc: 22 addr: 128 line: 4

If there are two caches, then we will consult the L2 cache only when the L1 cache misses. In that case,
the access to both affected caches should be logged separately, as follows:

L1 MISS pc: 22 addr: 128 line: 4
L2 HIT pc: 22 addr: 128 line: 0

In the above case, the read was a miss on L1, but hit on L2. Another situation to consider is when the
read misses on both caches.


程序代写代做C/C++/JAVA/安卓/PYTHON/留学生/PHP/APP开发/MATLAB


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