2024年6月13日

CS代考｜EGCP 520-01 Final Exam

这是一个CS代考的相关案例

Question 1

1 / 1 pts

What is the difference between R, I and J format instructions in MIPS? Give an example of each kind.

 

Question 2

4 / 4 pts

 

Consider the following four lines of code:

[0x4000] loop: beq $t0, $t1, exit

[0x4004] lw $s0, 0x20($s0)

[0x4008] add $t0, $t0, #1

[0x400C] j loop

exit

Assume t1 is 10, and s0 is 0x04.

For each line of code, clearly mention:

(a) Opcode

(b) Instruction type

(c) The field values in the 32 bit R/I/J instruction format.

 

Question 3

0.75 / 1 pts

 

Write at least two differences between a single-cycle, multicycle, and pipelined processor, along with an

advantage and disadvantage of each type.

 

Question 4

1 / 2 pts

 

(a) What are the three kinds of hazards in pipelined architecture?

(b) Point out the hazards in the following lines of code. It is possible for one or more kinds of hazards to

be not present in this code

[0x4000] loop: beq $t0, $t1, exit

[0x4004] lw $s0, 0x20($s0)

[0x4008] add $t0, $t0, #1

[0x400C] j loop

exit

 

Question 5

0.5 / 3 pts

 

(c) Draw clock cycle diagram for one complete iteration of this code

(d) Briefly describe two modifications you can introduce to reduce/remove data hazards. Redraw the

clock cycle diagram for either one of these two modifications.

(e) Briefly describe two modifications you can make to reduce/remove control hazards.

 

Question 6

 

Consider the same code snippet as before:

[0x4000] loop: beq $t0, $t1, exit

[0x4004] lw $s0, 0x20($s0)

[0x4008] add $t0, $t0, #1

[0x400C] j loop

exit

Assume t1 is 10, t0 is initialized to 0 and pipeline flushes for a pipeline flush is 10 cycles. Choose either

of the two modifications you proposed in the previous section to reduce data hazards.

(a) What is the speedup with and without this modification?

(b) What is the CPI with and without this modification?

 

Question 7

(a) Highlight the differences between direct-mapped, N-way set associative and fully associative cache.

(b) You want to build a cache that can accommodate 64 words on a 32bit system. Fill in the following

table, assuming 1 validity bit: