Verilog代写｜CSE 141L Course Project
Your task this quarter is to design a custom processor that supports specific Forward Error
Correction (FEC) tasks. FEC is commonly used in radio communications with lossy links where
retransmission is expensive, challenging, or impractical (as well as other domains). As an
interesting and motivating example, consider one of the longer-lived computational systems
humanity has ever built, the Voyager Probe, which passed out of the heliosphere last year but is
still sending us data! As an example closer to home, satellite radio streams allow for 4-5s of
signal loss (e.g. driving under a highway underpass) without any interruption in the audio
stream. Sirius receivers use a custom chip, historically the STA210/240, which is in many ways
simply an advanced form of what you are designing and implementing in this course.
Your instruction set architecture shall feature fixed-length instructions 9 bits wide.
Your ISA specification should describe:
• What operations it supports and what their respective opcodes are.
o For ideas, see the MIPS, ARM, RISC-V, and/or SPARC instruction lists
• How many instruction formats it supports and what they are
o In detail! How many bits for each field, where they are found in the instruction.
o Your instruction format description should be detailed enough that someone
other than you could write an assembler (a program that creates machine code
from assembly code) for it. (Again, refer to ARM or MIPS.)
• Number of registers, and how many general-purpose or specialized.
• All internal data paths and storage will be 8 bits wide.
• Addressing modes supported
o This applies to both memory instructions and branch instructions.
o How are addresses constructed or calculated? Lookup tables? Sign extension?
Direct addressing? Indirect? Immediates?
Some Things to Think About
For instructions to fit in a 9-bit field, the memory demands of these programs will have to be
small. For example, you will have to be clever to support a conventional main memory of 256
bytes (8-bit address pointer). You should consider how much data space you will need before
you finalize your instruction format. Your instructions are stored in a separate memory, so that
your data addresses need be only big enough to hold data. Your data memory is byte-wide, i.e.,
loads and stores read and write exactly 8 bits (one byte). Your instruction memory is 9 bits
wide, to hold your 9-bit machine code.
You will write and run three programs on your ISA. You may assume that the first starts at
address 0, and the other two are found in memory after the end of the first program (at some
nonoverlapping address of your choosing). The specification of your branch instructions may
depend on where your programs reside in memory, so you should make sure they still work if
the starting address changes a little (e.g., if you have to rewrite one of the programs and it
causes the others to also shift). This approach will allow you to put all three programs in the
same instruction memory later on in the quarter.
Architecture Limitations and Requirements
We shall impose the following constraints on your design, which will make the design a bit
1. Your core should have separate instruction memory and data memory.
2. You should assume single-ported data memory (a maximum of one read or one write
per instruction, not both — Your data memory will have only one address pointer input
port, for both input and output).
3. You should also assume a register file (or whatever internal storage you support) that
can write to only one register per instruction.
a. The sole exception to this rule is that you may have a multibit ALU condition/flag
register (e.g., carry out, or shift out, sign result, zero bit, etc., like ARM’s Z, N, C,
and V status bits) that can be written at the same time as an 8-bit data register, if
b. You may read more than one data register per cycle.
c. Your register file will have no more than two output ports and one input port.
d. You may use separate pointers for reads and writes, if you wish.
e. Please restrict register file size to no more than 16 registers.
4. Manual loop unrolling of your code is not allowed – use at least some branch or jump
5. Your ALU instructions will be a subset of those in ARMsim, or of comparable complexity.
6. You may use lookup tables / decoders, but these are limited to 16 elements each (i.e.,
pointer width 1, 2, 3, or 4 bits).
a. You may not, for example, build a big 512-element, 32-bit LUT to map your 9-bit
machine codes into ARM- or MIPS-like wider microcode. (It was amusing the first
time a team tried it, but it got old J.)