VHDL代写 | CSE 260M Laboratory #5

本次美国CS代写EE主要是VHDL电路设计

CSE 260M Laboratory #5

In this laboratory, you will implement an embedded RSRC computer system starting with VHDL models for the RSRC CPU (rsrc.vhd) and associated subcomponents, a Read-Only Memory (eprom.vhd), a Static Random-Access Memory (sram.vhd), and an I/O “PINS” module (pins.vhd). The top level module, testbench.vhd, is a hierarchical “wrapper” that “wraps up” these components into an embedded RSRC system for the Digilent Artix-7 development board. Each of these components, as well as the assembly language syntax for the RSRC CPU, the memory map for the embedded system, etc., will be discussed in detail during class lectures.

The machine language program in eprom.vhd supplied by the instructor computes the peak value of the polynomial from Labs 1-4 and displays the result in hexadecimal on the 7-segment display on the development board using the logic inside the PINS module. The assembly source code used to produce eprom.vhd is shown below:

.org 0
la r30,PINS la r31,TOP la r1,0
lar r2,1000001 la r3,-6
la r4,-30
la r5,-24

TOP: add r1,r1,r2 add r2,r2,r3 add r3,r3,r4 add r4,r4,r5

brpl r31,r2 nop
st r1,0(r30) stop

.org -4 PINS: .dw1

; Program starts at address 0
; IO addresses to r30
; r31 holds the loop address
; Initialize difference engine coefficients

; Update the difference engine values

; Branch conditionally to TOP testing for peak ; Replace with bin2bcd r1,r1
; Display the lower 8 BCD digits

In this laboratory, you will modify the appropriate RSRC source files to add a new instruction, bin2bcd, to the RSRC instruction set with the following syntax:

bin2bcd ra,rc

You will then replace the NOP instruction in the eprom.vhd file with a hand-assembled machine code for the instruction (use OP Code 00111 for the bin2bcd instruction):

bin2bcd r1,r1

so that when rebuilt your new embedded system displays the lower eight BCD digits of the peak value on the 7-segment display (the upper two BCD digits will be ignored in this lab).

STEP 1

Create a new Vivado project by following the steps in the “Laboratory 5 Tutorial” precisely.

STEP 2

Reproduce the simulation in the tutorial, and take a screen shot showing the myreg register in the PINS module being updated to 02d4ceff (HEX) at exactly 73,840 ns.

STEP 3

Modify alu.vhd to add the binary-to-bcd conversion functionality needed for the new bin2bcd instruction. Do this by adding a new input, bin2bcd, to the entity that indicates that the C output should be driven by the BCD version of the B input. Base your ALU modification on your solution to Lab 3.

STEP 4
Modify control.vhd appropriately to implement the functionality needed by bin2bcd.
STEP 5
Modify rsrc.vhd appropriately to implement the functionality needed by bin2bcd.
STEP 6
Synthesize your modified embedded system implementation and fix any warnings or errors. STEP 7

Repeat the simulation of STEP 2 to make sure the myreg register is updated with the BCD version of the peak value instead of the hexadecimal value, that is, make sure the bin2bcd instruction executes properly. If it is, proceed to STEP 8. If not, use the simulator to debug your design. You may have to add the control FSM, the register file, the ALU, or other components to the simulation in order to find your “bug.”

Save a copy of your final simulation for submission. STEP 8

Once you have a valid simulation, synthesize and implement your design and generate a BIT file for submission. Make sure your modifications did not introduce any new warnings or errors. This is very, very important. You must fix any warnings or errors before submitting your materials for grading.

STEP 9
Submit the following materials via Canvas for grading:

  1. 1)  Modified alu.vhd
  2. 2)  Modified control.vhd
  3. 3)  Modified rsrc.vhd
  4. 4)  Y our testbench.bit
  5. 5)  A “Zipped” copy of your entire Vivado project folder
  6. 6)  The simulation screen shot from STEP 2
  7. 7)  The simulation screen shot from STEP 7

GRADING RUBRIC

Correctly modified alu.vhd source*: 20% Correctly modified control.vhd source*: 20% Correctly modified rsrc.vhd source*: 10% Correctly functioning testbench.bit file: 20% Correctly “Zipped” Vivado project folder**: 10% Simulation screen shot from STEP 2: 10% Simulation screen shot from STEP 7: 10%

*These files will also be submitted in your “Zipped” Vivado project folder, but they must also be submitted individually to aid in grading.

**Files must be added to the Vivado project folder as outlined in the “Laboratory 5 Tutorial” to receive full credit for this part of the lab. Project folders without the source files at the top level of the folder hierarchy, for example, will result in a point deduction. Be careful not to point Vivado to files that are not in the folder when you add them to the project. The instructor may, in some cases, open your Vivado project as he grades your laboratory. If your Vivado project is not created as outlined in the tutorial, in many cases it will be impossible for the instructor to open your project (resulting in a point deduction).


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