For this assignment you are required to
- Demonstrate your understanding of datapath, pipelined datapath and processor architectures.
- Perform memory design, measure and improve cache performance and demonstrate your understanding of virtual memory.
- Learning outcomes
This assessment is relevant to the Course Learning Outcomes CLOs 4-5.
- Assessment details
This assessment will determine your ability to
- Understand the concepts taught over Week 5 to Week 8 of the course.
- Work independently in self-directed study to research the identified issues.
Prepare the answers to this assignment in an electronic format and convert to a single Acrobat PDF (.pdf) file for submission, with the filename being your student number (e.g., S1234567.pdf) containing all the answers to all the questions in this assignment.
Paper submissions are not accepted. Handwritten assignments are not accepted.
You should submit your assignment via Canvas Assignments Assignment 2 Submission. You may resubmit the assignment if you need to, only the most recent version will be marked. Please note the following.
Question 2 – Datapath and pipelining performance (25 marks)
For the pipelined datapath, there are FIVE stages: IF, ID, EX, MEM and WB. Assume that each of stages has the following latencies:
a) (3 x 5 = 15 marks) Briefly explain what each stage does. You need to identify the functional units involved such as PC, adder, instruction memory, register file, ALU and data memory.
b) (10 marks) Work out the ideal performance gain of the pipelined datapath over the nonpipelined datapath. Clearly show your working and reasoning.
Question 3 – Processor architectures (15 marks)
You are a processor designer. You are tasked to design a processor for smartphones as well as supercomputers. You have two architecture choices: RISC and CISC.
a) (6 marks) For smartphones, explain the reasons that you want to use RISC for your design and the concerns that you may have.
b) (9 marks) For supercomputers, explain the reasons why you want to use and not use RISC.
Question 4 – Memory system design (20 marks)
You are asked to design a memory system that is fast and affordable. You have decided to take advantage of locality and memory hierarchy for your design.
a) (8 marks) Clearly explain the effect of locality in terms of memory access. Give code examples for your explanation (do not use the example in the lecture notes).
b) (12 marks) Clearly explain how locality and memory hierarchy work together to give a fast and affordable memory system.
Question 5 – Cache performance (20 marks)
For a cache system with the following parameters:
Instruction cache (I-cache) miss rate = 1.5%
Data cache (D-cache) miss rate = 3%
Miss penalty = 100 cycles
Percentage of load & store instructions (the instructions that need D-cache): 30%
a) (15 marks) If it takes 1 clock cycle to complete an instruction without cache misses, that is, cycles per instruction (CPI) is 1, what is the percentage of time that CPU will spend on memory stalls? Show your working.
b) (5 marks) Briefly discuss how multilevel cache design improves cache performance,assuming a two-level cache.
本网站支持淘宝 支付宝 微信支付 paypal等等交易。如果不放心可以用淘宝交易！
E-mail: firstname.lastname@example.org 微信:itcsdx